The present invention relates to a data communications system; and, more particularly, to a method for effectively compensating a phase delay of a clock signal used in the data communications system.
In a data communications system having a microprocessor or an application specific integrated circuit (ASIC), there is normally employed an external memory for temporarily storing various information and operating or processing data of the system. When a semiconductor device such as processor(s) or device(s) in the system requests the external memory to retrieve any data stored therein, the external memory reads and transfers the data to the requesting device.
To synchronously read and transfer the data, generally, there is utilized a clock signal with a certain clock rate in the data communications system. Specifically, the clock signal is generated by a clock generator in the system and supplied to the semiconductor device requesting the retrieval of the data as well as the external memory via a bus so that they can be operated in synchronization with the clock signal.
Due to the usage of the bus between the semiconductor device and the external device and other factors in the data communications system, however, there necessarily exists a certain amount of delay in the clock signal to the external memory, resulting in a phase discrepancy in the clock signal supplied to each of the semiconductor device and the external memory. Such discrepancy may cause the retrieval of undesired data from the external memory, thereby lowering the reliability of the data communications system. Prior to storing data in the external memory, therefore, a simple clock test procedure has been carried out after initialization thereof.
To help understand the prior art clock test procedure, there is presented an ideal instance wherein clock signals to the semiconductor device and the external memory are synchronized. Details of a clock test procedure in the ideal instance will now be described with reference to FIGS. 3A to 3C. For simplicity, only one clock signal, CLK(C, M), is illustrated in FIG. 3A since no phase difference exists between the clock signals. It should be noted that the clock signal CLK(C, M) is not drawn in an actual scale.
First of all, the clock signal CLK(C, M) is applied to each of the semiconductor device and the external memory. When the clock signal CLK(C, M) is received by the semiconductor device, a controller, which is associated with the device and monitors the operation thereof, sequentially issues and transfers one or more test data signals and their corresponding address signals to the external memory via a bus in accordance with the clock signal CLK(C, M). The number of the test data signals can be determined based on the capacity of the external memory. For simplicity, in FIG. 3B, there are illustrated only two address signals A0 and A1, although their corresponding two test data signals D0 and D1 are not shown.
Specifically, at a rising edge t1 of the clock signal CLK(C, M), the controller produces and sends the test data signal D0 and the corresponding address signal A0 to the external memory via the bus. Meanwhile, the external memory, at a rising edge t2 of the clock signal CLK(C, M), receives and stores the test data signal D0 in an area that is indicated by the signal A0. And then, at a rising edge t4 of the clock signal CLK(C, M) after three cycles from the issuing of the test data signal D0 and the address signal A0 at the time t1, the controller again provides the external memory with the address signal A0 together with a control signal (not shown) to retrieve its corresponding data signal, i.e., D0, stored thereon. The time duration between said t1 and t4 can be decided on the basis of the performance and capacity of the data communications system and the external memory. In response to the address signal A0 and the control signal, the external memory, at a rising edge t5 of the clock signal CLK(C, M), reads and transfers the corresponding data signal D0 to the controller via the bus.
Thereafter, the controller, at a predetermined time, receives a data signal from the external memory and checks whether the test data signal D0 and the received data signal are the same. That is, at a rising edge t6 of the clock signal CLK(C, M) after two cycles from the issuing of the address signal A0 and the control signal at the time t4, the controller receives a data signal through the bus from the external memory and checks whether or not the test data signal D0 and the received data signal are the same. In this ideal instance, as can be seen from FIGS. 3A and 3C, it will be checked to be positive since both data signals are the same at the time t6. Regarding the test data signal D1 following the test data signal D0, the clock test procedure will be performed in the same manner. As can be inferred from the above test, since it will be checked to be positive with respect to all the test data signals, the controller finally determines the clock signal as a definitive one to be used in the semiconductor device and the external memory. However, if it is checked to be negative with respect to any of the test data signals during the clock test procedure, a conventional phase delay compensation procedure is carried out, as will be described below.
Turning now to FIGS. 4A to 4D, there are depicted timing diagrams for explaining the prior art clock test method. First, it is assumed that a clock signal CLK(C) as shown in FIG. 4A is applied to the semiconductor device, while a clock signal CLK(M) of FIG. 4C is inputted to the external memory. From FIG. 4C, it will be seen that there exists a phase delay of At in the clock signal CLK(M) compared to the clock signal CLK(C) for the reasons mentioned above.
The prior art clock test method is carried out in a same manner as in the ideal instance except that there are employed the two clock signals with a phase difference of At therebetween. In synchronization with the clock signal CLK(C) of FIG. 4A, first, the controller sequentially issues and sends one or more test data signals and their corresponding address signals to the external memory via the bus. For brevity, in FIG. 4B, there are illustrated only two address signals A0 and A1; but their corresponding two test data signals D0 and D1 are not shown.
Specifically, at a rising edge t1 of the clock signal CLK(C), the controller produces and sends the test data signal D0 and the corresponding address signal A0 to the external memory via the bus. Meantime, at a rising edge m1 of the clock signal CLK(M), the external memory receives and stores the test data signal D0 at an area to which the signal A0 corresponds. And then, at a rising edge t4 of the clock signal CLK(C) after three cycles from the issuing of the test data D0 and the address signal A0 at the time t1, the controller again produces and sends the address signal A0 together with a control signal(not shown) to the memory to retrieve its corresponding data signal, i.e., D0, stored thereon. In response to the signal A0 and the control signal, the memory, at a rising edge m4 of the clock signal CLK(M), reads and transfers the corresponding data signal D0 to the controller via the bus.
Thereafter, the controller, at a predetermined time, receives a data signal from the memory and checks as to whether the test data signal D0 and the received data signal are same. In other words, at a rising edge t6 of the clock signal CLK(C) after two cycles from the issuing of the address signal A0 and the control signal at the time t4, the controller receives a data signal from the external memory and checks whether or not the test data signal D0 and the received data signal are the same. In this case, as can be seen from FIGS. 4A and 4D, it will be checked to be negative since the data signal D0 transferred from the external memory is received by the controller at a rising edge t5 of the clock signal CLK(C). Regarding the test data signal D1 following the test data signal D0, the clock test procedure will be performed in the same manner. Through the above test, if it is checked to be positive with respect to all the test data signals, the controller finally determines the clock signal as a definitive one to be used in the semiconductor device and the external memory; however, if otherwise, i.e., if it is checked to be negative with respect to any of the test data, a conventional delay compensation technique is carried out in the following manner.
Normally, the amount of delay of the clock signal in the data communications system increases as the length of the bus lengthens. Based on this premise, the conventional delay compensation technique adjusts the length of the bus in accordance with the result from the clock test, thereby compensating the phase delay of the clock signal to the external memory. This technique, however, has a shortcoming in that it is incapable of adaptively arranging circuitry elements at their required positions within the semiconductor device.
It is, therefore, a primary object of the present invention to provide a method capable of improving the performance and reliability of a data communications system employing an effective phase delay compensation technique.
In accordance with the present invention, there is provided a method, for use in a data communications system having a semiconductor device and a storage device coupled thereto via a bus, for compensating a phase delay of a clock signal coupled to the devices, the method comprising the steps of:
(a) providing a plurality of delayed clock signals with different delay amounts by modifying the amounts of delay of the clock signal;
(b) in synchronization with a delayed clock signal selected among the delayed clock signals, sequentially issuing and sending, at a controller, one or more test data signals and address signals thereof to the storage device via the bus;
(c) in synchronization with the original clock signal, at the storage device, storing each of the one or more test data signals in an area that its address signal indicates and, thereafter, upon receipt of the address signal at a predetermined time of the original clock signal, reading and sending a data signal which corresponds to the address signal to the controller via the bus;
(d) at a predetermined time of the delayed clock signal, receiving, at the controller, a data signal from the storage device and checking as to whether or not said each test data signal and the received data signal are the same;
(e) if it is checked to be positive with respect to said each test data signal at said step (d), repeating said steps (b) to (d) for a next test data signal and, if otherwise, repeating said steps (b) to (d) for a next selected delayed clock signal until it becomes checked to be positive; and
(f) if it is checked to be positive with respect to all the one or more test data signals at said step (e), determining the delayed clock signal as a definitive clock signal to be used in the semiconductor device, and, if otherwise, repeating the steps (b) to (e) for a next selected delayed clock signal until it becomes checked to be positive.